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CDP1822, CDP1822C
March 1997
256-Word x 4-Bit LSI Static RAM
Description
The CDP1822 and CDP1822C are 256-word by 4-bit static random-access memories designed for use in memory systems where high speed, low operating current, and simplicity in use are desirable. The CDP1822 features high speed and a wide operating voltage range. Both types have separate data inputs and outputs and utilize single power supplies of 4V to 6.5V for the CDP1822C and 4V to 10.5V for the CDP1822. Two Chip-Select inputs are provided to simplify system expansion. An Output Disable control provides Wire-OR capability and is also useful in common Input/Output systems. The Output Disable input allows these RAMs to be used in common data Input/Output systems by forcing the output into a high-impedance state during a write operation independent of the Chip-Select input condition. The output assumes a high-impedance state when the Output Disable is at high level or when the chip is deselected by CS1 and/or CS2. The high noise immunity of the CMOS technology is preserved in this design. For TTL interfacing at 5V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input.
Features
* Low Operating Current - VDD = 5V, Cycle Time 1s . . . . . . . . . . . . . . . . . . 8mA * Industry Standard Pinout * Two Chip-Select Inputs-Simple Memory Expansion * Memory Retention for Standby Battery Voltage of 2V Minimum * Output-Disable for Common I/O Systems * Three-State Data Output for Bus-Oriented Systems * Separate Data Inputs and Outputs
Ordering Information
5V CDP1822CE 10V CDP1822E PACKAGE PDIP Burn-In SBDIP Burn-In -40oC to +85oC TEMP. RANGE -40oC to +85oC PKG. NO.
E22.4 E22.4 D22.4A D22.4A
CDP1822CEX CDP1822EX CDP1822CD CDP1822CDX CDP1822D -
Pinout
CDP1822, CDP1822C (PDIP, SBDIP) TOP VIEW
A3 1 A2 2 A1 3 A0 4 A5 5 A6 6 A7 7 VSS 8 DI1 9 DO1 10 DI2 11 22 VDD 21 A4 20 R/W 19 CS1 18 O. D. 17 CS2 16 DO4 15 DI4 14 DO3 13 DI3 12 DO2
OPERATIONAL MODES INPUTS CHIP SELECT 1 (CS1) 0 0 0 CHIP SELECT 2 (CS2) 1 1 1 OUTPUT READ/ DISABLE WRITE (OD) (R/W) 0 0 1 1 0 0
MODE Read Write Write
OUTPUT Read Data In High Impedance High Impedance High Impedance High Impedance
Standby
1
X
X
X
Standby
X
0
X
X
Output Disable NOTE:
X
X
1
X
Logic 1 = High, Logic 0 = Low, X = Don't Care.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1074.2
6-11
CDP1822, CDP1822C
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1822 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1822C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 80 21 Maximum Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC TA = -40oC to +60oC (Package Type E) . . . . . . . . . . . . . . 500mW TA = +60oC to +85oC (Package Type E) . . . . . . Derate Linearly at . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12mW/oC to 200mW Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . . 300oC
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges:
LIMITS CDP1822 PARAMETER DC Operating Voltage Range Input Voltage Range SYMBOL MIN 4 VSS MAX 10.5 VDD MIN 4 VSS CDP1822C MAX 6.5 VDD UNITS V V
Static Electrical Specifications
At TA = -40oC to +85oC, Except as Noted CONDITIONS CDP1822 LIMITS CDP1822C MAX 500 1000 0.1 0.1 1.5 3 5 10 MIN 2 -1 4.9 3.5 (NOTE 1) TYP 4 -2 0 5 MAX 500 0.1 1.5 5 UNITS A A mA mA mA mA V V V V V V V V A A
PARAMETER Quiescent Device Current Output Low (Sink) Current Output High (Source) Current Output Voltage Low-Level Output Voltage High-Level Input Low Voltage
SYMBOL IDD
VO (V) -
VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10
VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10
MIN 2 4.5 -1 -2.2 4.9 9.9 3.5 7 -
(NOTE 1) TYP 4 9 -2 -4.4 0 0 5 10 -
IOL
0.4 0.5
IOH
4.6 9.5
VOL
-
VOH
-
VIL
0.5, 4.5 0.5, 9.5
Input High Voltage
VIH
0.5, 9.5 0.5, 9.5
Input Leakage Current
IIN
-
6-12
CDP1822, CDP1822C
Static Electrical Specifications
At TA = -40oC to +85oC, Except as Noted (Continued) CONDITIONS CDP1822 PARAMETER Operating Current (Note 2) Three-State Output Leakage Current Input Capacitance Output Capacitance NOTES: 1. Typical values are for TA = +25oC and nominal VDD. 2. Outputs open circuited; Cycle time = 1s. SYMBOL IDD1 VO (V) IOUT 0, 5 0, 10 CIN COUT VIN (V) 0, 5 0, 10 0, 5 0, 10 VDD (V) 5 10 5 10 MIN (NOTE 1) TYP 4 8 5 10 MAX 8 16 5 10 7.5 15 MIN LIMITS CDP1822C (NOTE 1) TYP 4 5 10 MAX 8 5 7.5 15 UNITS mA mA A A pF pF
Dynamic Electrical Specifications
At TA + -40 to +85oC, VDD 5%, Input t R, t F = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD , CL = 100 pF TEST CONDITIONS CD1822 LIMITS CDP1822C MAX (NOTE 1) MIN (NOTE 2) TYP MAX UNITS
PARAMETER Read Cycle Times (Figure 1) Read Cycle tRC
VDD (V)
(NOTE 1) MIN
(NOTE 2) TYP
5 10
450 250 20 20 20 20 20 20
250 150 250 150 250 150 -
450 250 450 250 450 250 200 110 -
450 20 20 20 -
250 250 250 -
450 450 450 200 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Access from Address
tAA
5 10
Output Valid from Chip-Select 1
tDOA1
5 10
Output Valid from Chip-Select 2
tDOA2
5 10
Output Valid from Output Disable tDOA3
5 10
Output Hold from Chip-Select 1
tDOH1
5 10
Output Hold from Chip-Select 2
tDOH2
5 10
Output Hold from Output Disable tDOH3
5 10
NOTES: 1. Time required by a limit device to allow for indicated function. 2. Typical values are for TA = 25oC and nominal VDD.
6-13
CDP1822, CDP1822C
tRC
A0 - A7
CHIP-SELECT 1
tDOA1
tDOH1
CHIP-SELECT 2
tDOA2
tDOH2
OUTPUT DISABLE
tDOA3
tDOH3
READ/WRITE tAA
DATA OUT HIGH IMPEDANCE
DATA OUT VALID
HIGH IMPEDANCE
FIGURE 1. READ CYCLE TIMING WAVEFORMS
Dynamic Electrical Specifications
At TA + -40 to +85oC, VDD 5%, Input t R, t F = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD , CL = 100 pF. LIMITS CD1822 (NOTE 1) MIN (NOTE 2) TYP MAX (NOTE 1) MIN CDP1822C (NOTE 2) TYP MAX UNITS
TEST CONDITIONS PARAMETER Read Cycle Times (Figure 2) Write Cycle tWC 5 10 Address Setup tAS 5 10 Write Recovery tWR 5 10 Write Width tWRW 5 10 Input Data Setup Time tDS 5 10 Data Hold tDH 5 10 Chip-Select 1 Setup tCS1S 5 10 Chip-Select 2 Setup tCS2S 5 10 500 300 200 110 50 40 250 150 250 150 50 40 200 110 200 110 VDD (V)
-
-
500 200 50 250 250 50 200 200 -
-
-
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
6-14
CDP1822, CDP1822C
Dynamic Electrical Specifications
At TA + -40 to +85oC, VDD 5%, Input t R, t F = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD , CL = 100 pF. (Continued) LIMITS CD1822 (NOTE 1) MIN 0 0 0 0 200 110 (NOTE 2) TYP MAX (NOTE 1) MIN 0 0 0 0 200 CDP1822C (NOTE 2) TYP MAX UNITS ns ns ns ns ns ns
TEST CONDITIONS PARAMETER Chip-Select 1 Hold tCS1H VDD (V) 5 10 Chip-Select 2 Hold tCS2H 5 10 Output Disable Set-Up tODS 5 10 NOTES: 1. Time required by a limit device to allow for indicated function. 2. Typical values are for TA = 25oC and nominal VDD.
tWC tWR A0-A7
tCSIS CHIP-SELECT 1
tCSIH
CHIP-SELECT 2 tCS2S (NOTE) tODS DI1-DI4 tDS DATA IN STABLE tDH tCS2H
OUTPUT DISABLE
READ/WRITE tAS
tWRW
DON'T CARE
NOTE: tODS is required for common I/O operation only. For separate I/O operations, output disable is don't care. FIGURE 2. WRITE CYCLE TIME WAVEFORMS
6-15
CDP1822, CDP1822C
Data Retention Specifications
At TA = -40 to +85oC, see Figure 3. LIMITS TEST CONDITIONS PARAMETER Min. Data Retention Voltage Data Retention Quiescent Current Chip Deselect to Data Retention Time Recovery to Normal Operation Time VDD to VDR Rise and Fall Time VDR IDD tCDR tRC tR, tF 2 5 10 5 10 5 600 300 600 300 1 600 600 1 ns ns ns ns A VDR (V) 2 VDD (V) MIN CDP1822 (NOTE 1) TYP 1.5 30 MAX 2 100 MIN CDP1822C (NOTE 1) TYP 1.5 30 MAX 2 100 UNITS V A
NOTE: Typical values are for TA = 25oC and nominal VDD.
VDD
DATA RETENTION MODE DATA IN 0.95 VDD VDR tCDR CS2 VIH VIL tf tr tRC VIH VIL WRITE ADDRESS DECODER 0.95 VDD DATA OUT READ ADDRESS DECODER VDD
VSS
VDD
FIGURE 3. LOW VDD DATA RETENTION TIME WAVEFORMS
FIGURE 4. MEMORY CELL CONFIGURATION
6-16
CDP1822, CDP1822C
A0 A1 A2 A3 A4
4 3 2 1 21
(5) INPUT BUFFERS AND ALL ROWS DESELECT FUNCTION
(32) ROW 22 DECODERS
VDD
DI1 DI2 DI3 DI4
9 11 13 15
(4) GATES
(8 x 32) STORAGE ARRAY
(8 x 32) STORAGE ARRAY
(8 x 32) STORAGE ARRAY
(8 x 32) STORAGE ARRAY
(4) BITS (1-4) BUFFER DRIVERS 10
D01 12 D02 14 D03 16 D04
BIT (1)
BIT (2)
BIT (3)
BIT (4)
(8) A5 A6 A7
(8) COLUMN DECODERS
(8) COLUMN DECODERS
(8) COLUMN DECODERS
5 6 7
(3) INPUT BUFFERS AND ALL COLUMNS DESELECT FUNCTION
COLUMN DECODERS
R/W
20
CONTROL B 8
CSI CS2 OD
19 17 18
VSS
CONTROL A
CONTROL C
VDD
VDD
VDD
VSS
VSS
VSS
INPUT PROTECTION
NETWORK
OUTPUT
PROTECTION CIRCUIT
OVER VOLTAGE
PROTECTION CIRCUIT
FIGURE 5. FUNCTIONAL BLOCK DIAGRAM FOR CDP1822 AND CDP1822C
6-17
CDP1822, CDP1822CS
C
CONTROL A CS1 19 A CHIP-SELECT CONTROL
CS2 17
CONTROL B R/W 20 B CHIP-SELECT AND R/W CONTROL
CONTROL C C OUTPUT DISABLE CONTROL
OUTPUT 18 DISABLE
FIGURE 6. LOGIC DIAGRAM OF CONTROLS FOR CDP1822 AND CDP1822C
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
6-18

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